Deep sub-micron effects can be magnified by shrinking feature sizes, which can result in integrated circuits being prone to timing-related defects. Accordingly, stringent test quality requirements have favored the use of at-speed testing procedures in addition to traditional static test procedures that target stuck-at faults. While at-speed functional patterns used to be an alternative in targeting timing-related defects, increasing design complexity has hampered the generation and utilization of functional patterns, which has instead favored the use of scan-based structural at-speed testing techniques.
In full-scan designs, a structural at-speed pattern can be loaded into the scan cells via scan operations, and subsequently, applied to the circuit. As the targeted defects can be timing-related, these patterns typically check whether transitions launched from scan cells can arrive at their destinations (e.g., scan cells) within a functional clock period.
There are generally two different schemes for launching transitions off a serially loaded pattern. In launch-off-capture (“LOC” or broadside) test (see, e.g., Reference 1), a functional capture operation typically launches transitions from the locations where the serially loaded pattern V1 differs from the response of the combinational logic to V1 (e.g., the launch pattern V2). In launch-off-shift (“LOS” or skewed-load) test (see, e.g., Reference 2), a single-cycle shift operation typically launches transitions from the locations where the serially loaded pattern V1 differs from its one-bit shifted version (e.g., the launch pattern V2 ). In both schemes, a subsequent fast functional capture operation, which can be of a functional clock period apart from the launch event, can set a deadline for the transitions to arrive at their destinations. A timing-related defect that slows down the chip below its rated clock speed can therefore be exposed. Neither scheme is generally capable of bringing any arbitrary launch pattern V2 into the scan cells due to the constraint in which the launch pattern can be generated out of the serially loaded pattern V1 . Transition fault or path delay coverage loss can ensue as a result.
Serial shift operations during a scan can result in excessive switching activity in the scan chains, which can propagate into the combinational logic, and which can further unnecessarily dissipate dynamic power in both static and at-speed testing schemes. The end-result, unless treated properly, can be an unexpected behavior of the design, thereby resulting in, for example, a yield loss or reliability problems. Elevated levels of peak power, which can be the maximum instantaneous power throughout the entire test process, can be the cause of the former problem, while the underlying reason for the latter problem can be average power, which can be the total power dissipation averaged over the duration of the test application process. (See, e.g., References 3, 4). As the test application process is typically dominated by shift operations, average power can mostly depend on shift power, and thus, the impact of capture power on average power can generally be negligible. Capture power, however, can typically be more of a concern when peak power is the targeted issue.
Yield loss problem can be further exacerbated in at-speed testing schemes. (See, e.g., References 5, 6). Excessive switching activity during the launch cycle can result in elevated peak supply currents, which can lead to IR drop that can increase signal propagation delays in the combinational logic. The end-effect may not be differentiated from that of a timing-related defect, causing a functional chip to fail the at-speed test. Peak power during the launch cycle of at-speed testing can be preferably reduced in order to avoid the yield loss induced by IR drop.
Some research effort has been performed in order to reduce power dissipation during the launch and capture of at-speed testing; these techniques generally target the LOC scheme. Test pattern generation, while accounting for the functional clock gating logic in order to produce patterns that disable parts of the design during launch and capture, has been proposed (see, e.g., References 7, 8) in order to reduce peak power at the expense of pattern count inflation. Another approach that elevates pattern count while reducing peak launch power has been in the form of generating patterns under the constraint that only one chain launches transitions while all chains capture. (See, e.g., Reference 9). A partitioning approach has been proposed (see, e.g., Reference 10), where power-wise costly patterns are further analyzed via fault simulation to identify the location of the care bits, which dictates the partitioning of the design during capture; with few problematic patterns. Such an approach can deliver power savings, albeit at the expense of ancillary defect coverage loss as the analysis can be fault model dependent. A judicious x-fill approach driven by an analysis of the responses repetitively produced by the combinational logic has been proposed (see, e.g., Reference 11); as with other x-fill approaches, pattern count inflation can be the side effect. Another x-fill approach (see, e.g., Reference 12) can retain pattern count and fault coverage, however, it cannot guarantee the same level of defect coverage. Partitioning the design, and testing one partition at a time, has been proposed to reduce launch and capture power in BIST (see, e.g., Reference 13), in LOS (see, e.g., Reference 14), and in LOC (see, e.g., Reference 15) testing schemes. In these schemes, newly generated patterns targeting one partition at a time typically end up loading the interface registers of other partitions as well, incurring test time and data volume penalty. A similar end-result has been experienced even when the design can be partitioned via ILP that minimizes capture violations (see, e.g., Reference 16). For such violations, additional test patterns, possibly of a high sequential depth, are typically need to be generated so as to cover the faults missed due to capture violations, while possibly leaving some of the unmodeled defects uncovered.
While LOC can attain lower fault coverage levels compared to LOS, both schemes can suffer from over-testing of chips as they can lead the design to a functionally unreachable state upon loading a pattern. Additionally, LOS suffers more from over-testing, as the launch event can also be performed via a shift operation, which can be non-functional at higher run-times, as the identification of the proper V1-V2 pair typically requires two-time-frame test generation as opposed to a simpler single-bit shift relation between V1 and V2. Therefore, the LOS scheme can pose challenges. For example, in LOS, the scan-enable signal can switch from HIGH (shift mode) to LOW (capture mode) at-speed, and can be treated as a fast clock signal during timing closure. This problem can be alleviated however by proposed solutions. (See, e.g., References 17, 18). Additionally, as LOS can be capable of launching more transitions compared to LOC, which can be one of the reasons why LOS can deliver a higher coverage, power dissipation of LOS in the launch cycle can be higher than that in LOC. (See, e.g., References 7, 19).
Accordingly, there may be a need to address at least some of the above-described deficiencies.